This application relates to decoding signals that carry clock and data information. In particular, it relates to construction of a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval.
Biphase encoding is a family of digital codes used for transmission of audio signals and for communication. Biphase encoding is favored in noisy environments, where pulse edges are more easily and reliably detected than the peaks and troughs of pulses. Codes that rely on biphase encoding include the biphase mark code (BMC), the Manchester code and the differential Manchester code. Common to these codes, at least one transition (or pulse edge) occurs for each data bit and, sometimes, two transitions. The presence of transitions in the bits, even if a string of ones are zeros is repeated, allows biphase encoding to reliably carry both clock information and data. Further discussions of these codes can be found in Wikipedia, in the general category of “line codes” and specifically articles for “biphase mark code”, “Manchester code” and “differential Manchester code.”
Biphase encoding facilitates so-called clock recovery and synchronization. The signal encoded typically is time sensitive, such as samples from an audio stream. Reconstruction of the original signal from the encoded signal is time dependent. The encoded signal is delivered asynchronously, so the source and the decoder are operating with different clocks. The source clock can be recovered from the encoding, because every bit (with exceptions related to framing) includes a transition that can be used to recover a clock edge. The decoder synchronizes its clock with the source clock using logic such as an analog phase lock loop or a digitally controlled oscillator.
Biphase codes belong to a more general family of balanced or grey codes with limited run lengths. These codes are balanced in the sense of being DC balanced; the DC offset from cumulative codes is either zero or a specific proportion of the bits in the code stream. In this application, when we refer to a code as having a limited run length or as being run length limited, we mean a code that ensures that within n bits there will be a transition between a “0” and “1” bit, either 0/1 or 1/0. Generally, n is less than or equal to 20. Commonly, n is less than or equal to 10. Encodings that result in shorter maximum lengths of running zeros or ones, run lengths limited to 9, 8, 7, 6, 5 and 4 bits, are described in the patents that have been incorporated by reference.
Illustrations of biphase encoding are given in FIG. 1. A clock is represented at the top of the figure, followed by data in both waveform and numeric representations. Four encoding examples follow, representing a biphase mark code, variations on the Manchester code that represent a “zero” as either a rising or falling edge, and a differential Manchester code. In the biphase mark code, every bit of the original data is represented as two logical states which, together, form a bit. A “one” in the input is represented by two unequal states (10 or 01). A “zero” in the input is represented by two equal states (00 or 11). A transition or edge defines the beginning and end of a data bit. The particulars of encoding data using other biphase encoding rules are easily found in Wikipedia and elsewhere. A common application of biphase encoding is audio transfer. The Sony-Philips Digital Interconnect Format (SPDIF or S/PDIF), typically used for home applications, combines the biphase mark code with a particular preamble that violates the biphase encoding rules once per frame, in the preamble. SPIDF framing is specified in the worldwide standard IEC958 1989-03 (consumer part) from the EBU, which has a Japanese counterpart EIAJ CP-340 1987-9. See “SPIDF” accessed at http://www.epanorama.net/documents/audio/spidf.html on Jan. 4, 2009. In this application, we refer collectively to these standards for a digital audio interface, their predecessors and successors as the “SPIDF standard.” The SPIDF standard for consumers is compatible with the AES/EBU standard for professional audio work. The consumer and professional standards differ primarily in sub code information and physical connectors. Both standards support 24-bit sample resolution.
According to these standards, samples are transmitted as 32-bit words or sub frames. These bits are used as follows:
bitsmeaning0-3 Preamble4-7 Auxillary-audio-databits8-27Sample28Validity29Sub code-data30Channel-status-information31Parity (bit 0-3 are not included)
A 24- or 16-bit sample can be used. The 24-bit sample value uses bits 4-27. A CD-player uses only 16 bits, so only bits 13-27 are used, and bits 4-12 are set to 0.
One set of problems with decoding arises from jitter and drift. By jitter we mean instantaneous deviations from the intended clock frequency. Jitter has historically been a problem with point-to-point digital audio interfaces, as explained in the paper, Frandsen, C., and M. Lave. “Plug and Play? an Investigation into Problems and Solutions of Digital Audio Networks.” AES116th Convention. Berlin, May 8-11, 2004. Accessed at <http://www.tcelectronic.com/TechLibrary.aspcfm> on Jan. 4, 2009. Among the products tested in that review, a receiver with jitter rejection of +/−10 ppm from −20 C to 70 C and +/−5 ppm per year would lock to only about half of the tested products, due to jitter. Id., at p. 7 & p. 12 table 9. Drift is less well defined. By drift, we mean relatively slow changes in the source clock frequency, such as 50-60 or 100-120 hertz changes, which can vary the position of data bits by more than a whole data bit interval, far outside the published jitter tolerance required of grade one or two devices.
An example of the phase lock loop (PLL) approach to jitter rejection and synchronization can be seen in U.S. Pat. No. 6,901,127, issued to Margules. The PLL is reference 18 in Margules' FIG. 1. FIGS. 4-5 further depict adjusting the PLL and maintaining lock.
An alternative approach can be seen in U.S. Pat. No. 5,889,820, issued to Adams. The technology described by Adams uses a digitally controlled oscillator in order to lock onto the timing of the biphase mark encoded input data. Another digitally controlled clock is described in U.S. Pat. No. 6,768,433 issued to Toth. All three of the Margules, Adam and Toth patents strive to synchronize and phase lock the source and decoder clocks, in support of decoding a biphase mark code input stream.
It should be apparent that there is an opportunity to introduce technology that has favorable jitter rejection characteristics, particularly technology that can handle both jitter and drift.